1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor optical device, and more particularly to a method for manufacturing a semiconductor optical device in which the waveguide ridge has an electrode on its top.
2. Description of the Related Art
There has been a need for emission of light in the blue to ultraviolet wavelength range to enhance the recording density of optical discs. In order to meet such a need, intense R&D effort has recently been carried out to develop nitride semiconductor lasers formed of a Group III-V nitride compound semiconductor such as AlGaInN. Some of them have already been practically used.
Such blue-violet laser diodes (hereinafter referred to as “blue-violet LDs”) are formed by growing a compound semiconductor in crystal form on a GaN substrate.
A representative compound semiconductor is the Group III-V compound semiconductor, in which Group III and V elements are combined together. Mixed crystal III-V compound semiconductors having different compositions can be formed by bonding pluralities of Group III atoms and Group V atoms in different manners. Examples of compound semiconductors used to form a blue-violet LD include GaN, GaPN, GaNAs, InGaN, and AlGaN.
In ridge waveguide LDs, an electrode layer is usually provided on top of the waveguide ridge. This electrode layer is connected to the contact layer (i.e., the top layer of the waveguide ridge) through an opening formed in the insulating film covering the top portion of the waveguide ridge. This insulating film with the above opening is formed by lift-off using the same resist mask that was used to form the waveguide ridge. However, since the surface of the resist mask in contact with the contact layer is concavely curved with respect to the surface of the contact layer, part of the material used to form the insulating film covering the waveguide ridge remains in this concave portion and hence partly covers the surface of the contact layer even after the lift-off process, resulting in a reduction in the contact area between the electrode layer and the contact layer. That is, the contact area is smaller than the top surface area of the contact layer.
In the case of a red LD, this reduction in the contact area between the electrode layer and the contact layer due to the lift-off process does not significantly increase the contact resistance and hence the operating voltage of the LD, since the material used to form the contact layer (e.g., GaAs, etc.) has a relatively low contact resistance.
In the case of a blue-violet LD, on the other hand, the material used to form the contact layer is GaN, etc. having a relatively high contact resistance. Therefore, a reduction in the contact area between the electrode and the contract layer results in an increase in the contact resistance between them, thereby increasing the operating voltage of the blue-violet LD.
There will now be described several known methods for manufacturing an LD in such way as to prevent a reduction in the contact area between the electrode and the contact layer.
A first method forms a nitride semiconductor laser device in the following manner. First, a p-type electrode layer of palladium/molybdenum/gold is formed on a p-type contact layer which is the top layer of the semiconductor layer stack formed on a wafer. A resist mask (not shown) having a stripe shape is then formed on the p-type electrode layer and used to form a ridge stripe by RIE (Reactive Ion Etching). More specifically, the p-type electrode is formed by etching using Ar gas, and then the p-type contact layer and the p-type cladding layer, or these layers and the p-guiding layer, are etched by a mixed gas composed of Ar, Cl2, and SiCl4 to form the ridge stripe. (The etching is stopped at a depth halfway through the p-type cladding layer or the p-guiding layer.) Next, an insulating film (of Zr oxide predominantly including ZrO2) having a thickness of 0.5 μm is formed over the surface of the wafer with the ridge strip still leaving the resist thereon. The resist is then removed to expose the top surface of the ridge stripe. Further, a p-type pad electrode of molybdenum and gold is formed to cover the p-type electrode and at least the portions of the insulating film on both sides of the p-type electrode. (See, e.g., Japanese Domestic Republication of International Patent Application No. WO 2003/085790, lines 42-50 on page 9, FIG. 1.)
A second known method is a self-aligning method for manufacturing a ridge waveguide semiconductor LD and includes the step of forming two different photoresist layers one on top of the other, as described below.
The lower photoresist layer is only sensitive to light of wavelengths shorter than 300 nm, while the upper photoresist layer is only sensitive to light of wavelengths longer than 300 nm. Specifically, this self-aligning method is applied to a laminated semiconductor structure that includes a second cladding waveguide layer and a capping layer formed on the second cladding waveguide layer. The method begins by removing portions of the capping layer and the second cladding waveguide layer to form a ridge structure and a double channel. A second insulating film is then formed on the surfaces of the ridge structure and the double channel. A first photoresist layer (the lower photoresist layer) is then formed on the second insulating film, and a second photoresist layer (the upper photoresist layer) is formed on the first photoresist layer. Next, the second photoresist layer is patterned to expose the portions of the first photoresist layer around the ridge structure. Further, the first photoresist layer is processed by an RIE process to expose the portion of the second insulating film on the ridge structure. The portions of the second insulating film around the ridge structure are then removed by an etching process including an RIE process. The remaining portions of the first and second photoresist layers are then removed, and a first metal layer is deposited as an electrode. (See, e.g., Japanese Laid-Open Patent Publication No. 2000-22261, paragraphs 0024 to 0034, FIGS. 7 to 18.)
A third known method first forms a ridge and channels by wet etching the contact layer using a metal mask of Al and then wet etching the underlying layer using as a mask this contact layer with the metal mask still thereon. Next, an insulating film is formed over the entire surface of the substrate by plasma CVD, and the Al pattern (the metal mask) and the overlying portions of the insulating film are removed by lift-off. A resist pattern is then formed by a common lithographic process. (This resist pattern exposes the portion of the surface where a p-type electrode is subsequently formed.) A layer of electrode material is then formed by vacuum deposition using the resist pattern as a mask, and subsequently the resist pattern and the overlying portion of the electrode material layer are removed by lift-off to form the electrode in close contact with the contact layer of the ridge. (See, e.g., Japanese Laid-Open Patent Publication No. 2000-340880, paragraphs 0025 to 0034, FIG. 1.)
A fourth known method proceeds as follows. A first protective film is formed over substantially the entire surface of the p-side contact layer, and a third protective film having a stripe shape is formed on the first protective film. Then, after etching the first protective film with the third protective film thereon, the third protective film is removed. Then the first protective film having a stripe shape is formed. The p-side contact layer is then etched through its entire thickness and the underlying layer (for example, a p-side cladding layer) is etched halfway through its thickness to form a waveguide having a stripe shape. Next, a second protective film (which has electrically insulating properties and is made of a different material than the first protective film) is formed on the sides of the stripe-shaped waveguide and on the top surface of the nitride semiconductor layer (i.e., the p-side cladding layer) exposed by the above etching process. The first protective film is then removed by lift-off, and a p-electrode is formed on the second protective film and the p-side contact layer such that the p-electrode is electrically connected to the p-side contact layer. (See, e.g., Japanese Laid-Open Patent Publication No. 2003-142769, paragraphs 0020 to 0027, FIG. 1.)
The above conventional methods provide a sufficient contact area between the contact layer of the waveguide ridge and the electrode layer. However, these methods are disadvantageous in that it is difficult to reliably manufacture devices having substantially equal characteristics, since they include the step of: etching a metal film and the underlying semiconductor layer at the same time; etching the lower of two laminated resist layers to a predetermined controlled depth; or forming an electrode by lift-off after forming a metal film mask or a plurality of protective films. Furthers employing a plurality of resists or protective films results in reduced freedom in process design.
In order to overcome the above problems, a method has been proposed for manufacturing a semiconductor optical device in such a way to reliably prevent a reduction in the contact area between the top semiconductor layer (or contact layer) of the waveguide ridge and the overlying electrode layer by employing a simple process.
This method proceeds as follows. Channels are formed in a wafer having a semiconductor layer stack formed thereon, thereby forming a waveguide ridge. An SiO2 film is then formed over the entire surface of the wafer. A resist is then applied over the entire surface of the wafer to form a resist film having a greater thickness on the channels than on the top of the waveguide ridge. Next, material is uniformly removed by dry etching from the surface of the resist film so that the film is completely removed from on top of the waveguide ridge but left in the channels, thereby forming a resist pattern that exposes the top of the waveguide ridge but left in the channels. The exposed surface of the SiO2 film is then uniformly etched using the resist pattern as a mask so that the film is completely removed from on top of the waveguide ridge but left on the sides and bottoms of the channels. The remaining portion of the SiO2 film has an opening that exposes the top of the waveguide ridge.
Then, after removing the resist pattern, a p-side electrode is formed on the top of the waveguide ridge.
Several known processes for forming a ridge will now be described. A first known process forms a ridge stripe using a p-type ohmic electrode as a mask in the following manner. First, a stripe-shaped metal layer stack (including a first layer of Ni/Au and a second layer of Pt) is formed on the top surface of the p-contact layer of GaN. The wafer is then heat treated to alloy these metal layers to form the p-side ohmic electrode. Next, the wafer is etched in an etching gas of Cl2 using the p-side ohmic electrode as a mask until the p-type guiding layer is exposed. (See, e.g., Japanese Laid-Open Patent Publication No. 2004-253545, paragraphs 0035 to 0038, FIG. 2.)
A second known process for forming a ridge proceeds as follows.
At a first step, a first protective film of an Si oxide is formed over substantially the entire surface of the p-side contact layer, and a stripe-shaped third protective film is formed on the first protective film. The first protective film with the third protective film thereon is then etched into a stripe shape, and the third protective film is removed.
At a second step, the portions of the p-side contact layer and the p-side cladding layer which are not covered by the first protective film are etched to form a stripe-shaped waveguide region corresponding to the shape of the first protective film under the first protective film.
At a third step, a second protective film (which has electrically insulating properties and which is made of a different material than the first protective film) is formed on the sides of the stripe-shaped waveguide, on the etched and exposed top surface of the nitride semiconductor layer (i.e., the p-side cladding layer), and on the first protective film. The first protective film and the overlying portion of the second protective film on the first protective film are then removed by etching, leaving the second protective film on the sides of the stripe-shaped waveguide and the top surface of the p-side cladding layer. The remaining portion of the second protective film continuously extends from the sides of the stripe to the top surface of the p-side cladding layer.
The etching at the above third step may be, but is not limited to, dry etching using hydrofluoric acid. (See, e.g., Japanese Laid-Open Patent Publication No. 2000-114664, paragraphs 0018 to 0024, FIG. 6.)
A third known process for forming a ridge proceeds as follows.
First, layers of GaN-based material are epitaxially grown on a sapphire substrate, and a first SiO2 film (a first mask) having a stripe shape is formed on the top layer (a p-GaN contact layer). Dry etching is then performed using the first SiO2 film as a mask to form a ridge stripe.
Next, an AlGaN burying layer is uniformly formed on both sides of the ridge stripe and on the first SiO2 film, and a second SiO2 film (a second mask) is formed on the AlGaN burying layer. A resist film is then formed on the second SiO2 film by spin coating such that the resist film has a smaller thickness on the top of the ridge stripe than on both sides of the ridge stripe. The portion of the resist film above the top of the ridge stripe is removed by dry etching using oxygen gas, etc. to expose the second SiO2 film (or second mask). Subsequently, the exposed portion of the second SiO2 film is selectively etched using CF4 to expose the AlGaN burying layer. The remaining resist film is then removed by ashing to expose the second SiO2 film. The AlGaN burying layer is then partially removed by wet etching using the second SiO2 film as a mask to expose the first SiO2 film (or first mask) on the top of the ridge stripe. Lastly, the first SiO2 film (or first mask) and the second SiO2 film (or second mask) are removed by wet etching. (See, e.g., Japanese Laid-Open Patent Publication No. 2000-164987, paragraphs 0030 to 0040, FIGS. 2 to 12.)
Further, a fourth known process for forming a ridge proceeds as follows.
First, a laminated structure of GaN-based material is formed on a sapphire substrate by MOCVD, etc., and a stripe-shaped second electrode is formed on the second contact layer of the laminated structure. A ridge structure is then formed using this second electrode as a mask. Next, an SiO2 insulating film is formed to entirely cover the ridge structure and the second cladding layer on both sides of the ridge structure (the ridge structure including the second electrode, the second contact layer, and a portion of the second cladding layer). A resist film is then applied over this insulating film such that the resist film has a smaller thickness on the ridge structure than on both sides of the ridge structure. The top surface of the resist film is substantially flat and level. Etching is then performed to expose the top surface and both sides of the second electrode and the upper portions of both sides of the contact layer and thereby form a stripe-shaped metal film having a width corresponding to the width of the mesa structure. (See, e.g. Japanese Laid-Open Patent Publication No. 2002-335048, paragraphs 0064 to 0073, FIGS. 3 to 6.)
Thus, conventional methods for manufacturing an optical semiconductor device include the following steps: channels are formed in a wafer, thereby forming a waveguide ridge; an SiO2 film is formed over the entire surface of the wafer; a resist is applied over the SiO2 film to form a resist film; a material is removed from the surface of the resist film so that the film is completely removed from on top of the waveguide but left in the channels, thereby forming a resist pattern that exposes the top of the waveguide ridge; and the exposed surface of the SiO2 film is uniformly etched using the resist pattern as a mask so that the SiO2 film is completely removed from on top of the waveguide ridge but left on the sides and bottoms of the channels (that is, the remaining portion of the SiO2 film has an opening that exposes the top of the waveguide ridge). In the above last step, if dry etching is used to remove the SiO2 film from on top of the waveguide ridge, the semiconductor layer underlying the SiO2 film may be damaged under certain circumstances. For example, when the underlying semiconductor layer is a p-type contact layer, it may be damaged by the etching process, resulting in an increased contact resistance. Especially, if the p-type contact layer is made of a GaN-based material, the damaged portion(s) is difficult to remove by wet etching, since it is difficult to remove GaN-based material from a surface by wet etching.